Static random access memory (SRAM) integrated circuits are a popular type of computer memory devices, and have become even more popular in recent years with the advent of high speed and high density complementary metal-oxide-semiconductor (CMOS) technology. Conventional SRAM memory cells are commonly configured as a latch of cross-coupled inverters, each inverter usually having an n-channel drive transistor with either a resistive or active load. SRAM cells using resistor loads are commonly referred to as 4-T, 2-R cells (corresponding to four transistors and two resistors in each cell, including the bit line transfer devices). It is well known that the standby power of SRAM cells decreases with increasing load resistance, as the DC current drawn through the inverter having its n-channel pull-down transistor on will depend on this resistance. It is well known that the use of a p-channel transistor as an active load in a CMOS SRAM cell can provide extremely low standby current, as the p-channel transistor in a CMOS inverter is turned off (and is thus extremely resistive) when the n-channel device is on. Accordingly, where CMOS technology is available, use of a p-channel MOS transistor as the load can provide extremely low standby currents. SRAM cells which utilize p-channel load devices are commonly referred to as six-transistor, or 6-T, cells.
However, many CMOS SRAMs are manufactured having resistors as load devices, despite the availability of p-channel transistors elsewhere in the circuit. This is primarily due to the additional chip area required to include both n-channel and p-channel transistors in each memory cell. Formation of both an n-channel and a p-channel transistor in the single crystal semiconductor (substrate or epitaxial layer) requires not only active regions of both n-type and p-type, but also the provision of isolation regions therebetween. Isolation is particularly critical for SRAM cells, due to the stringent standby current specifications (making junction leakage intolerable), and to the need to avoid latchup conditions. As a result, more chip area is required for implementing a 6-T CMOS SRAM cell, including both types of active regions and the isolation therebetween for each memory cell, relative to the chip area required for a 4-T, 2-R SRAM cell. This has caused many manufacturers to implement resistor loads in the memory cells of their CMOS SRAMs.
Prior work has been directed to reducing the area required for CMOS inverters, or CMOS half-latches as useful in SRAM cells, by way of thin-film transistors. So-called "stacked" CMOS inverters which include an n-channel transistor in single crystal silicon, and a p-channel transistor in a polysilicon layer (or recrystallized polysilicon) thereover, with a common gate electrode therebetween, are described in U.S. Pat. No. 4,502,202 and U.S. Pat. No. 4,814,850, and in Malhi, et al., "A VLSI Suitable 2-.mu.m Stacked CMOS Process", Device Research Conference, Paper VB.1 (IEEE, 1984). In addition, Malhi, et al., "Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon," IEEE Transactions on Electron Devices, Vol. ED-32, No. 2 (Feb. 1985), pp. 258-281 describes, particularly at pages 273 through 277, an implementation of an 6-T SRAM cell including stacked CMOS inverters.
By way of further background, U.S. Pat. No. 4,777,147 discloses a CMOS inverter which includes a self-aligned polysilicon n-channel driver transistor formed into a single crystal substrate. A polysilicon layer (annealed to single crystal at locations overlying the substrate) electrically connects to the drain of the n-channel transistor, and extends over isolation oxide, with source and drain regions doped thereinto in a self-aligned manner on either side of an overlying gate electrode, so as to form a thinfilm transistor over the isolation oxide which is connected to the n-channel drive transistor.
By way of still further background, U.S. Pat. No. 4,890,148 discloses an SRAM cell which uses gated thin film resistors as load devices. According to this disclosed SRAM cell, polysilicon resistors are provided which are separated from polysilicon/silicide gate electrodes by a relative thin insulating layer; the polysilicon resistors are also doped on one end with n-type dopant. The configuration of the SRAM cell is such that the gate of one of the n-channel drive transistors serves as the gate of the opposite load device, so that a high voltage thereon will turn on (i.e., cause conduction) through one n-channel drive transistor and through the opposite gated resistor.
It is an object of this invention to provide a six-transistor CMOS SRAM cell which requires a relatively small amount of chip area.
It is a further object of this invention to provide such an SRAM cell which utilizes thin-film transistors.
It is a further object of this invention to provide such an SRAM cell which utilizes complementary polysilicon load devices for each half latch.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.